ASIC Design and Verification in an FPGA Environment

Dejan Markovic, Chen Chang, Brian Richards, Hayden So, Borivoje Nikolic, Robert W. Brodersen
2007 2007 IEEE Custom Integrated Circuits Conference  
A unified algorithm-architecture-circuit co-design environment for dedicated signal processing hardware is presented. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This unified description enables system designer with a visibility through several layers of design hierarchy down to circuit level to select the optimal architecture. The tool flow propagates up
more » ... el performance and power estimates to rapidly evaluate architecture-level tradeoffs. The common Simulink design description minimizes errors in translation of the design between different descriptions, and eases the verification burden. The FPGA used for emulation can be used as a low-cost tool for testing of the fabricated ASIC. The approach is demonstrated on an ASIC for 4×4 MIMO signal processing.
doi:10.1109/cicc.2007.4405836 dblp:conf/cicc/MarkovicCRSNB07 fatcat:rgr3d5ppx5hvfo5jgrxlczwvta