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A CMOS low-IF programmable gain amplifier with speed-enhanced DC offset cancellation

Chao-Shiun Wang, Po-Chiun Huang
Proceedings. IEEE Asia-Pacific Conference on ASIC,  

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This paper presents a programmable gain amplifier for dual band (GSM900/DCS1800) low-IF receiver. It is a negative feedback approach to achieve high linearity requirement. In addition to the amplifier, anti-alias filtering and dc offset removal are included for the following IF signal processing. A dual-bandwidth algorithm is developed to speed up the settling time on DC removal. A modified Sallen-Key filter helps on providing better than 40dB anti-aliasing and blocker attenuation near the
more » ... ing frequency 13MHz. The overall PGA gain varies from 0dB to 46dB with 2dB per step. With a 0.25µm CMOS process, this work dissipates 10.3mW from a 2.7V supply voltage.
doi:10.1109/apasic.2002.1031550 fatcat:hkppmaburndspcv5nrk7wlbrom
Citation

Chao-Shiun Wang, Po-Chiun Huang. "A CMOS low-IF programmable gain amplifier with speed-enhanced DC offset cancellation." Proceedings. IEEE Asia-Pacific Conference on ASIC,