Scavenger: A New Last Level Cache Architecture with Global Block Priority

Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jose Martinez
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of intervening misses at the last-level cache between the eviction of a particular block and its reuse can be very large, preventing traditional victim caching mechanisms from exploiting this repeating behavior. In this paper, we present Scavenger, a new architecture for last-level caches. Scavenger divides the total storage
more » ... udget into a conventional cache and a novel victim file architecture, which employs a skewed Bloom filter in conjunction with a pipelined priority heap to identify and retain the blocks that most frequently missed in the conventional part of the cache in the recent past. When compared against a baseline configuration with a 1MB 8-way L2 cache, a Scavenger configuration with a 512kB 8-way conventional cache and a 512kB victim file achieves an IPC improvement of up to 63% and on average (geometric mean) 14.2% for nine memory-bound SPEC 2000 applications. On a larger set of sixteen SPEC 2000 applications, Scavenger achieves an average speedup of 8%
doi:10.1109/micro.2007.42 dblp:conf/micro/BasuKKCM07 fatcat:4wuxz6mqcjh4hhywwemfy2x26i