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Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements
2005
Proceedings of the 42nd annual conference on Design automation - DAC '05
Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multistream access with different QoS requirements is involved. In [8], a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard realtime constraints for periodic video signals and hard real-time
doi:10.1145/1065579.1065729
dblp:conf/dac/HeitheckerE05
fatcat:t3u7vpngzrdrxfwdsc5irlamym