Automatic Memory Reductions for RTL Model Verification

Panagiotis Manolios, Sudarshan Srinivasan, Daron Vroon
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
Motivation ∎ Pipelined machine verification ▮ State of the art: term level models ▮ The major limitation ▮ We really want to verify RTL-level models ▮ RTL models too hard for state of the art ▮ We developed BAT, Bit-level Analysis Tool PC RF DM IM
doi:10.1109/iccad.2006.320121 fatcat:bclh4fkmdzhjdbb766aly4hypy