Intelligate: Scalable Dynamic Invariant Learning for Power Reduction [chapter]

Roni Wiener, Gila Kamhi, Moshe Y. Vardi
2009 Lecture Notes in Computer Science  
In this work we introduce an enhanced methodology to detect dynamic invariants from a power-benchmark simulation trace database. The method is scalable for the application of clock-gating extraction on industrial designs. Our approach focuses upon dynamic simulation data as the main source for detection of opportunities for power reduction. Experimental results demonstrate our ability to learn accurate clock-gating functions from simulation traces and achieve significant power reduction (in the
more » ... range of 30%-70% of a clock net's power) on industrial micro-processor designs. Introduction Power consumption has become a major concern for modern microprocessor designs; it affects battery life in the mobile segment, and limits chip frequency in desktops and servers. In this context, a significant design effort is spent on reducing power dissipation, aiming at delivering maximum performance per watt. Power dissipation has a dynamic component, due to the switching of active devices, and a static component, due to the leakage of inactive devices. Since our work targets dynamic power only, further references to "power" in this paper imply the dynamic component. The clock network is known to be one of the major power consumers, accounting for 30%-40% of the total power of a chip [1]. This can be explained by the large capacitance of the clock net elements, together with their high switching activity. Clock gating is one of the most effective and widely used techniques for saving clock power. If a logic block does not perform any useful computation, one can stop the clock of the block, thus saving switching activity and dynamic power [2] . We can classify the existing approaches based on the type of gating conditions. Unobservability conditions, or ODCs ("Observable Don't Cares"), were used in [3] to gate state elements that are not observed by their environment. Stability conditions, or STCs [4], were proposed in [5] to gate state elements that are stable at the same value. ODCs constitute a natural candidate for clock gating, since they can be computed and expressed as combinational conditions. A scalable ODC-based approach is used in [3]
doi:10.1007/978-3-540-95948-9_6 fatcat:e53kxaeek5hkxohocplxilhwqe