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LUTNet: Rethinking Inference in FPGA Soft Logic
[article]
2019
arXiv
pre-print
Research has shown that deep neural networks contain significant redundancy, and that high classification accuracies can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation.
arXiv:1904.00938v1
fatcat:2rclxhsodvbqpitblbmy3ipkfq