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Thermal mapping of interconnects subjected to brief electrical stresses
1997
IEEE Electron Device Letters
The failure of metal interconnects subjected to brief electrical-current pulses is a reliability concern for the integrated circuits industry, especially in connection with electrostatic discharge (ESD). Since the magnitude and spatial distribution of the temperature rise during pulsing events strongly influence these failures, the development of suitable thermometry techniques is needed to understand the failure. This work reports scanning laser-reflectance thermometry with a novel calibration
doi:10.1109/55.641429
fatcat:4zlf3uazcnacxhyefw6d5zpbvi