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ReVIVaL
2008
SIGARCH Computer Architecture News
Process variations are poised to significantly degrade performance benefits sought by moving to the next nanoscale technology node. Parameter fluctuations in devices can introduce large variations in peak operation among chips, among cores on a single chip, and among microarchitectural blocks within one core. Hence, it will be difficult to only rely on traditional frequency binning to efficiently cover the large variations that are expected. Furthermore, multiple voltage/frequency domains
doi:10.1145/1394608.1382138
fatcat:mka36s3glfby5cesynittpn4fa