Adaptation of DSP Processors for 3G and 4G Wireless Communication
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Technological advancements have resulted in significant changes in the processor architecture of mobile phones, transforming the typical mobile phones of 1990's to modern smart phones. The next generation of mobile computing requirements will increase due to higher data rates, increased complexity algorithms, and greater computation diversity but the power requirements will be just as stringent to ensure reasonable battery lifetimes.The design of the next generation of mobile platforms must
... ess three critical challenges: efficiency, programmability, and adaptivity. This paper presents analysis of mobile signal processing applications and advanced signal processing architectures to deal with the rigorous requirements. This paper illustrates the role of Digital Signal Processors for Third generation (3G) mobile systems and DSP architectures for 4G wireless communication. Base Band Modem: The 3G standard is expected to be an essential factor that enables applications involving the transmission of wideband signals. Rake,Channel-Encoding/Decoding Hardware-Software Tradeoffs: Because of the variability of the parameters, datarates, and memory referencing, these functions are ideally suited to DSP for manipulation Glueless Homogeneous and Heterogeneous Multiprocessing: The TigerSHARC DSP provides several options for high-speed communication, including on-chip DMA (direct memoryaccess) and SDRAM support, along with dedicated user programmable link ports. B. DSP Architectures for 3G Mobile Communications Systems: The choice of a DSP to obtain the required computation speed is not a direct matter of specifying the highest clock speed Architecture and instruction sets greatly affect the speed of algorithm execution. "MIPS"(millions of instructions per second). Another aspect to consider is the class of DSP architecture employed. Two recently introduced new classes to consider are: very long instruction word (VLIW) and static superscalar .VLIW tries to reduce cost and increase execution speed by reducing hardware complexity. The sequencing mechanism in VLIW depends on an instruction format. In VLIW, all operation latencies in a particular implementation are fully open to software. The TMS320C6x series from Texas Instruments is an example of VLIW architecture. Static superscalar architectures apply a consistent and functionally well-defined programming model, and the schedule is determined prior to run time. The TigerSHARC™ DSP from Analog Devices is an example of a static superscalar architecture. The TigerSHARC Architecture The TigerSHARC DSP  as shown in figure 3(a) permits multiple instructions per line and therefore reduces the overall cycle count required to perform 3G related functions such as channel decoding, de-spreading, and path searches. Since the acceleration capabilities reside in software rather than in static hardware blocks or coprocessors, TigerSHARC DSPs provide the flexibility, scalability, and interoperability needed in today's highly competitive market. TigerSHARC DSP provides all the processing capacity to enable a single high speed 3G data channels. Qualcomm Snapdragon Processors Snapdragon is a family of mobile system on a chip (SoC) processor architecture provided by Qualcomm. In the year 2013, Qualcomm Snapdragon 800 processor with Krait 400 CPU cores providing 2.3 GHz clock speed outperformed all other processors in the mobile segment.