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Reducing cache misses using hardware and software page placement
1999
Proceedings of the 13th international conference on Supercomputing - ICS '99
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been used to improve instruction and data cache performance for virtually indexed caches by mapping code and data with temporal locality to different cache blocks. In this paper we examine the performance of compiler and hardware approaches for reordering pages in physically addressed caches to eliminate cache misses. The
doi:10.1145/305138.305189
dblp:conf/ics/SherwoodCE99
fatcat:asdc5hmtxje6fotrvmpu6md23i