In the current and future System-On-Chips, a non-negligible part of operation time is spent on multiple-clock period wires. Retiming-that is moving flip-flops in a circuit without changing its functionality-can be explored to pipeline long interconnect wires in SOC designs. The problem of retiming over a netlist of macro-blocks, where the internal structures may not be changed and flip-flops may not be inserted on some wire segments is called the wire retiming problem. In this paper, we

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... e the constraints of the wire retiming problem as a fixpoint computation and use an iterative algorithm to solve it. Experimental results show that this approach is multiple orders more efficient than the previous one. Introduction With a great market drive for high performance and integration, operating frequencies and chip sizes of System-On-Chips (SOCs) are dramatically increasing. Industry data showed that the frequencies of high-performance ICs approximately doubled every process generation and the die size also increased by about 25% per generation. With such short clock periods, the communication among different blocks on a SOC circuit of ever increasing complexity is becoming a bottleneck: even with interconnect optimization techniques such as buffer insertion, the delay from one block to another may be longer than one clock period, and multiple clock cycles are generally required to communicate such a global signal. This trend has motivated recent research within Intel [1] and IBM [5] on how to insert flip-flops on a given net if the communication between the pins requires multiple clock cycles. However, inserting flip-flops within a circuit will change its functionality, and inserting arbitrary number of them on a net without considering global consistency will destroy the correctness of a circuit. Retiming [8] is a traditional sequential optimization technique that moves flip-flops within a circuit without destroying its functionality. In traditional settings, retiming was used mainly on gate level netlists. Although some recent research incorporated wire delays in retiming [7, 11] , they did not consider the situation where multiple flip-flops may be on a global interconnect. This paper explores the alternative utility of retiming-that is, besides its computational function, a flipflop can be used to fulfill communication buffering requirements. Since dominant wire delays can only happen on global wires, we solve the problem at the chip level, that is, the design we deal with is a netlist of macro-blocks. The wires within a block are relatively much shorter thus do not need multiple clock periods for propagation. In SOC design, many of these macro-blocks are IP (Intellectual Property) cores. Some of these blocks may be combinational circuits, and others sequential. Because of the existence of pre-designed blocks such as IP cores or regular-structured blocks such as memories, (combinational) buffers or flip-flops may not be inserted everywhere [12] . Our previous work [9] used timing macro-models to model the timing behavior of the blocks and a set of integer difference inequalities was shown to be both necessary and sufficient, thus quantify a solution. A polynomial-time algorithm was given for feasibility checking under a given fixed clock period and based on that, a fully polynomial-time approximation scheme for clock period minimization was proposed.