Hardware Accelerator for Probabilistic Inference in 65-nm CMOS

Osama U. Khan, David D. Wentzloff
2016 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
A hardware accelerator is presented to compute the probabilistic inference for a Bayesian Network (BN) in distributed sensing applications. For energy efficiency, the accelerator is operated at a near-threshold voltage of 0.5V while achieving a maximum clock frequency of 33MHz. Clique-tree message passing algorithm is leveraged to compute the probabilistic inference. The theoretical maximum size of a factor that the proposed hardware accelerator can handle is 2 (8×20)=160 entries which is
more » ... ient for handling massive BNs such as PATHFINDER, MUNIN etc. (>1000 nodes). The ALARM Bayesian network is used to benchmark the performance of the accelerator. The accelerator consumes 76nJ to execute the ALARM network using a Clique-tree message-passing algorithm while the same algorithm executed on an ultra-low-power microcontroller consumes 20mJ. Index Terms-Bayesian Network, Clique-tree, embedded machine learning, hardware accelerator, intelligent sensor node, message passing, probabilistic graphical model, probabilistic inference.
doi:10.1109/tvlsi.2015.2420663 fatcat:hv6vl2hwnzberitviwsgmspjzq