A low-cost serial decoder architecture for low-density parity-check convolutional codes

S. Bates, Zhengang Chen, L. Gunthorpe, A.E. Pusane, K.Sh. Zigangirov, Daniel J. Costello
2008 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
We propose a low-cost serial decoder architecture for low-density parity-check convolutional codes (LDPC-CCs). It has been shown that LDPC-CCs can achieve comparable performance to LDPC block codes with constraint length much less than the block length. The proposed serial decoder architecture for LDPC-CCs uses a single decoding processor. Terminated data frames are sent through the processor iteratively until correctly decoded or a maximum number of iterations is reached. This architecture
more » ... s memory consumption and uses a very small number of logic elements, making it especially suitable for strong LDPC-CCs with large code memory. The proposed architecture is realized for a (2048,3,6) regular LDPC-CC on an Altera Stratix FPGA. With a maximum of 100 iterations, the design achieves up to 9-Mb/s throughput using only a very small portion of the field-programmable gate array resources.
doi:10.1109/tcsi.2008.918002 fatcat:2xgyexdltfbdfnh5vomkamxkvq