In recent years, computational capacity o f single Field Programmable Gate Array (FPGA) devices as well as their versatility have increased significantly. Adding to that fact, the High Level Synthesis frameworks allowing to program such processors in a high-level language like C + + , makes modern FPG A devices a serious candidate as building blocks o f a general-purpose High Performance Computing solution. In this contribution we describe benchmarks which we performed using a kernel from the

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... ttice Q C D code, a highly compute-demanding HPC academic code for elementary particle simulations on the newest device from Xilinx, the U250 accelerator card. We describe the architecture o f our solution and benchmark its performance on a single FPG A device running in two modes: using either external or embedded memory. We discuss both approaches in detail and provide assessment for the necessary memory throughput and the minimal amount o f resources needed to deliver optimal performance depending on the available hardware. Our considerations can be used as guidelines for estimating the performance of some larger, manynode systems.