Low Latency Pipelined Circular CORDIC

E. Antelo, J. Villalba
17th IEEE Symposium on Computer Arithmetic (ARITH'05)  
The pipelined CORDIC with linear approximation to rotation has been proposed to achieve reductions in delay, power and area; however, the schemes for rotation (multiplication) and vectoring (division) complicate implementation in a single unit. In this work, we improve the linear approximation scheme, leading to a unified implementation for rotation and vectoring where fully parallel tree multipliers are used instead of the second half of CORDIC iterations. We also combine the linear
more » ... on to rotation with the scale factor compensation so that the compensation is performed concurrently with the rotation process. Comparison with other designs is also provided.
doi:10.1109/arith.2005.30 dblp:conf/arith/AnteloV05 fatcat:wp75tdk22vfyjdx3fcyovn5z3a