A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2014; you can also visit the original URL.
The file type is application/pdf
.
A 3D SoC design for H.264 application with on-chip DRAM stacking
2010
2010 IEEE International 3D Systems Integration Conference (3DIC)
Three-dimensional (3D) on-chip memory stacking has been proposed as a promising solution to the "memory wall" challenge with the benefits of low access latency, high data bandwidth, and low power consumption. The stacked memory tiers leverage through-silicon-vias (TSVs) to communicate with logic tiers, and thus dramatically reduce the access latency and improve the data bandwidth without the constraint of I/O pin count. To demonstrate the feasibility of 3D memory stacking, this paper introduces
doi:10.1109/3dic.2010.5751446
dblp:conf/3dic/ZhangWFCLSXSDXCL10
fatcat:yd7dsapi3jc6vbh2mii4u7bc7m