Internet Archive Scholar

Low power Implementation of Fast Addition using Quaternary Signed Digit Number System

Golla Veera Chandrap, S Ahmed Bashap, P Prasad Babup, P Devannap, P Sudhakarp
2015 IJISET-International Journal of Innovative Science, Engineering & Technology   unpublished

Preserved Fulltext

fulltext thumbnail
Web Archive Capture PDF (614.9 kB)
https://web.archive.org/web/20180409232434/http://www.ijiset.com/vol2/v2s7/IJISET_V2_I6_82.pdf

A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL. The file type is application/pdf.

In With the binary number system, the computation speed is limited by formation and propagation of carry Perform carry free addition, borrow free subtraction and multiplication. However the QSD number system requires a different set of prime modulo based logic elements for each arithmetic operation. A carry free arithmetic operation can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD). In QSD, each digit can be represented by a number from-3 to 3. Carry free
more » ... ddition and other operations on a large number of digits such as 64, 128, or more can be implemented with constant delay and less complexity.
fatcat:vkavraf64zdrliubjywonjhgvu
Citation

Golla Veera Chandrap, S Ahmed Bashap, P Prasad Babup, P Devannap, P Sudhakarp. "Low power Implementation of Fast Addition using Quaternary Signed Digit Number System." IJISET-International Journal of Innovative Science, Engineering & Technology (2015)