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As CMOS technology down sized into double digit nanometer ranges, variations are a serious concern due to uncertainty in devices and interconnect characteristics. The single event upset (SEU) is changing the state of a memory cell due to the strike of an energetic particle. The single event multiple effects are likely to increase in nanometer CMOS technology due to reduced device size and scaling of power supply voltage.SRAM cells are sensitive to radiation induced hazards. Therefore, designingdoi:10.5120/ijca2016911429 fatcat:z5zpwrelvfgjpe6zjdwqxdc6oe