Relaxing Resource-Sharing Constraints for Improved Hardware Management and Schedulability

Bryan C. Ward
2015 2015 IEEE Real-Time Systems Symposium  
Modern computer architectures, particularly multicore systems, include shared hardware resources such as caches and interconnects that introduce timing-interference channels. Unmanaged access to such resources can adversely affect the execution time of other tasks, and lead to unpredictable execution times and associated analysis pessimism that can entirely negate the benefits of a multicore processor. To mitigate such effects, accesses to shared hardware resources should be managed, for
more » ... , by a real-time locking protocol. However, accesses to some hardware resources can be managed with more relaxed sharing constraints than mutual exclusion while still mitigating timing-interference channels. This paper presents two new classes of sharing constraints, preemptive mutual exclusion, and half-protected sharing, which are motivated by the sharing constraints of buses and caches, respectively. Synchronization algorithms are presented for both sharing constraints, where applicable, on both uni-and multi-processor systems. A fundamentally new analysis technique called idleness analysis is presented to account for the effects of blocking in globally scheduled multiprocessor systems. Experimental results suggest that these relaxed synchronization requirements and improved analysis techniques can improve schedulability by up to 250%. Furthermore, idleness analysis can be applied to existing locking protocols to improve schedulability in many cases.
doi:10.1109/rtss.2015.22 dblp:conf/rtss/Ward15 fatcat:542pnxpstnhgjbk4m2x7yp5ya4