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Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
2004
Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04
A technique for automatic insertion of slack matching buffers for performance enhancement in the asynchronous design style known as Phased Logic (PL) is described. A description of how slack matching buffers can offer throughput increases in PL circuitry is presented and is supported through the use of a simulation tool developed for modeling the timing behavior of PL circuits. A description of the architecture of the simulator and its implementation is also discussed. Based on the analysis of
doi:10.1145/988952.989051
dblp:conf/glvlsi/FazelLTRT04
fatcat:vy2fnpy24bbtxc6ox7pgkthpfy