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Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
<span title="">2004</span>
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<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cuck3arl5zcl5nv2jjpeyumj44" style="color: black;">Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04</a>
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A technique for automatic insertion of slack matching buffers for performance enhancement in the asynchronous design style known as Phased Logic (PL) is described. A description of how slack matching buffers can offer throughput increases in PL circuitry is presented and is supported through the use of a simulation tool developed for modeling the timing behavior of PL circuits. A description of the architecture of the simulator and its implementation is also discussed. Based on the analysis of
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... esults provided by the simulator and the topological characteristics of a PL circuit, an algorithm for automatic slack matching buffer placement is devised. Examples of the buffer insertion technique are given and the effectiveness of the technique is evaluated through a set of experimental results.
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