Design of an ASIC-Based High Speed 32-bit Floating Point Adder

Debarshi Deka, Navaneeth Kumar, Dipankar Pal
2021 2021 International Conference on Applied Electronics (AE)   unpublished
Advancements in machine-learning algorithms made it necessary to explore fast algorithms for Floating Point operations, addition being most commonly used complex operation involving significant delay and power-consumption. Applications include high-performance computer vision, imaging and deep-learning functions accelerated using dedicated hardware accelerators. This paper proposes a 32-bit Floating Point Adder based on the 'Far-and-Close-Data-Path-Algorithm' with added optimizations to give a
more » ... etter implementation in terms of overall minimum latency and improved accuracy for certain input cases. The designs have been coded in Verilog, synthesized in Cadence Genus and physically verified with Cadence Innovus in GDSII under ASIC platform.
doi:10.23919/ae51540.2021.9542881 fatcat:gj5isopcpnfmtexsff2bmtjlii