Needs for Multi-Level Interconnect Technology hanks to advanced scaling techniques over the past 20 years, device performance and operating speeds have skyrocketed. Clock frequencies already exceed 200 MHz in submicron RISC microprocessors. As the minimum feature size has continued to scale down to submicron proportions. however. minimum interconnect line widths and spac-ings have, of necessity, followed. As a result, interconnect performance has become a limiting factor impinging on circuit

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... formance. The RC delay of lines increase, and tend to limit the length of global routing. Crosstalk becomes a problem, and limits the scaling of metal pitches. The current densities also increase. approaching the electromigration limit. Ultimately, this class of performance bottlenecks transcend good 'circuit design. Clearly, improving interconnect performance is the key to reducing and controlling degradation within acceptable levels. Technology in memories, for example, has proceeded to the point where a new generation of SRAMs are expected every 2-3 years [I]. Their capacity will be in the Circuits & Devices 16 8755-3996/95/$4.000 I99SIEEE