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D-Latch has applications in Memory cells and Low power D-Latchs are important for low-power digital designs. In this paper, presents design of the low power & high speed D-Latch using carbon nanotube field effect transistor (CNTFET) that utilizes different threshold voltages for best performance. In this paper, proposed design of D-Latch is simulated with HSPICE models, cmos 32nm ptm and CNTFET 32nm which Presented by Stanford University. MOSFET and CNTFET designs are simulated in differentdoi:10.4314/jfas.v8i2s.171 fatcat:jtqnrdkfcne7xnn2gleui5u6ye