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Proceedings of 1994 IEEE Workshop on VLSI Signal Processing
The paper is concerned with the timing analysis of a class digital systems we call mixed asynchronous synchronous systems. In such a system, each computation module is either synchronous i.e. clocked or asynchronous i.e. selftimed. The communication between modules is assumed to be selftimed for all modules. We i n troduce a graph model called MASS for describing the timing behaviour of such architectures. The graph contains two kinds of nodes, synchronous and asynchronous nodes. The operationdoi:10.1109/vlsisp.1994.574735 fatcat:boat33hlb5ehfkvhp6fxux6hka