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Journal of Computers
The complexity in timing optimization of highperformance microprocessors has been increasing with the number of channel-connected transistors in various paths of dynamic CMOS circuits and the rising magnitude of process variations in nanometer CMOS process. In this paper, a process variation aware transistor sizing algorithm for dynamic CMOS circuits while considering the Load Balance of Multiple Paths (LBMP) is proposed. The proposed iterative optimization algorithm is a deterministic approachdoi:10.4304/jcp.3.2.21-28 fatcat:bkztetjmfrgn3plmwurgrwvche