A REVIEW OF EVOLUTION OF MODERN TESTBENCH ENVIRONMENT FOR VERIFICATION USING SV/UVM

Amulya M S, Sujatha Hiremath
2020 Zenodo  
In the recent years, there has been an exponential growth in design and complexity. The time taken to develop products and deploy them in the market has become a major parameter which gives a competitive edge to any developer. In the VLSI Design flow, Verification takes up almost 70% of the time and is the key to reducing time to market and improving products. Testbench environment established for verification purpose has been significantly improved over the past few years. The emergence of
more » ... em Verilog / Universal Verification Methodology (SV/UVM) has played a major role in this process. UVM ensures well defined standard protocols including parallel bus schemes such as AMBA, memory and communication interfaces such as Ethernet can be implemented with ease and interoperability. This paper discusses the evolution of the testbench environment with the rise of UVM. The modern testbench is designed to ensure ease of use for the designers and inter communication between UVM components in a standard framework.
doi:10.5281/zenodo.3864868 fatcat:ccuqc7lflrfk3epboya3k6egkq