A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes

Vishal Sharma, Santosh Vishvakarma, Shailesh Singh Chouhan, Kari Halonen
2018 International journal of circuit theory and applications  
In this work, a data-dependent feedback-cutting-based bit-interleaved 12T static random access memory (SRAM) cell is proposed, which enhances the write margin in terms of write trip point (WTP) and write static noise margin (WSNM) by 2.14× and 8.99× whereas read stability in terms of dynamic read noise margin (DRNM) and read static noise margin (RSNM) by 1.06× and 2.6 ×, respectively, for 0.4 V when compared with a conventional 6T SRAM cell. The standby power has also been reduced to 0.93× with
more » ... an area overhead of 1.49× as that of 6T. Monte Carlo simulation results show that the proposed cell offers a robust write margin when compared with the state-of-the-art memory cells available in the literature. An analytical model of WSNM for 12T operating in subthreshold region is also proposed, which has been verified using the simulation results. Finally, a small SRAM macro along with its independent memory controller has been designed. KEYWORDS circuit design, low-power, SRAM, stability, write ability Int J Circ Theor Appl. 2018;1-20. wileyonlinelibrary.com/journal/cta
doi:10.1002/cta.2555 fatcat:ogwqmylvznhivecclak7q3nvb4