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Previous work has suggested that "soft" synthesizable programmable logic cores can efficiently provide small amounts of post-fabrication flexibility to integrated circuits. Previous architectures restrict the circuitry assigned to the core to be combinational. In this paper, we present two methods to enhance these architectures to support sequential logic. We apply these methods to a previously developed fabric, and optimize and compare them. We also describe a proof-ofconcept chip employing one of our techniques.doi:10.1109/cicc.2004.1358844 dblp:conf/cicc/YanW04 fatcat:asvzkdyktbcqngmtnv4xd3ndn4