Combining CTL, trace theory and timing models [chapter]

Jerry R. Burch
1990 Lecture Notes in Computer Science  
i t t s b u r g h , PA 15213 A b s t r a c t A system that combines CTL model checking and trace theory for verifying speed-independent asynchronous circuits is described. This system is able to verify a large and useful class of liveness and fairness properties, and is able to find safety violations after examining only a small fraction of the circuit's state space in many cases. An extension has been implemented that allows the verification of circuits that are not speed-independent, but
more » ... ad rely on assumptions about the relative delays of their components for correct operation. This greatly expands the class of circuits that can be automatically verified, making the verifier a more useful toot in the design of asynchronous circuits. The system is demonstrated on several fair mutual exclusion circuits, including a speed-independent version that is verified correct. It is also shown that given quite weak assumptions about the relative delays of components, the problem of designing a fair mutual exclusion circuit using a potentially unfair mutual exclusion element becomes almost trivial.
doi:10.1007/3-540-52148-8_28 fatcat:ahztuveav5fn5l3e3ry23w5qd4