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Combining CTL, trace theory and timing models
[chapter]
1990
Lecture Notes in Computer Science
i t t s b u r g h , PA 15213 A b s t r a c t A system that combines CTL model checking and trace theory for verifying speed-independent asynchronous circuits is described. This system is able to verify a large and useful class of liveness and fairness properties, and is able to find safety violations after examining only a small fraction of the circuit's state space in many cases. An extension has been implemented that allows the verification of circuits that are not speed-independent, but
doi:10.1007/3-540-52148-8_28
fatcat:ahztuveav5fn5l3e3ry23w5qd4