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A MOS approach to CMOS DET flip-flop design
2002
IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
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A novel approach to double-edge-triggered (DET) flip-flop design is presented along with a new static flip-flop and a new dynamic flipflop. The approach builds CMOS circuits using pass transistors and MOSstyle clocked inverters and addresses issues of threshold voltage drop ( drop) and circuit complexity. Among DET designs, the number of switched and total transistors used by our flip-flops is less than or equal to any in related work. Our circuits beat all others in speed (maximum frequency
doi:10.1109/tcsi.2002.800837
fatcat:ruihbitelbedvmfbgra3x6fslq