Technology mapping issues for an FPGA with lookup tables and PLA-like blocks

Alireza Kaviani, Stephen Brown
2000 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00  
In this paper we present new technology mapping algorithms for use in a programmable logic device (PLD) that contains both lookup tables (LUTs) and PLA-like blocks. The technology mapping algorithms partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of LUTs and PLA-like blocks. Since no other technology mapping algorithm for this problem has been previously published, we cannot compare our approach to others. Instead, to illustrate the
more » ... nce of this problem we use our algorithms to investigate the benefits provided by a PLD architecture with both LUTs and PLA-like blocks compared to a traditional LUT-based FPGA. The experimental results indicate that our mixed PLD architecture is more area-efficient than LUT-based FPGAs by up to 29%, or more depth-efficient by up to 75%. 1
doi:10.1145/329166.329180 dblp:conf/fpga/KavianiB00 fatcat:36di7wxan5ecdiiexbrkzvzyfa