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A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime
2006
2006 International Conference on Field Programmable Logic and Applications
Preserved Fulltext
A reconfiguralbe device can be utilized to enhance speed and yield on the sub-100nm device technologies, in which large within-die (WID) variations will degrade speed and cause huge yield loss in conventional fixed-structured ASICs. In the proposed scheme, configurations of all fabricated chips are optmized according to measured intra variations of LUTs and switch matrixes. Two LSIs are fabricated in a 90nm CMOS process. We successfully measured WID variations on the first LUT array LSI. The
doi:10.1109/fpl.2006.311276
dblp:conf/fpl/KobayashiKKTOSO06
fatcat:zfhdn5mjs5b65aejlsqreva5vy