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To perform functional formal verification, model checking for assertions has attracted attentions. In SystemVerilog, assertions are allowed to include "local variables", which are used to store and refer to data values locally within assertions. For the purpose of model checking, a finite automaton called "checker" is generated. In the previous approach for checker generation by Long and Seawright, the checker introduces new state variables corresponding to a local variable. The number of thedoi:10.2197/ipsjtsldm.2.80 fatcat:5lutlzicxbeitebggbadeays3e