Checker Generation of Assertions with Local Variables for Model Checking

Sho Takeuchi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
2009 IPSJ Transactions on System LSI Design Methodology  
To perform functional formal verification, model checking for assertions has attracted attentions. In SystemVerilog, assertions are allowed to include "local variables", which are used to store and refer to data values locally within assertions. For the purpose of model checking, a finite automaton called "checker" is generated. In the previous approach for checker generation by Long and Seawright, the checker introduces new state variables corresponding to a local variable. The number of the
more » ... troduced state variables for each local variable, is linear to the size of a given assertion. In this paper, we show an algorithm for checker generation in order to reduce the number of the introduced state variables . In particular, our algorithm requires only one such variable for each local variable. We also show experimental results on bounded model checking for our algorithm compared with the previous work by Long and Seawright.
doi:10.2197/ipsjtsldm.2.80 fatcat:5lutlzicxbeitebggbadeays3e