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#AiMES2018_20181002_1400_Low-T-SiGe_Porret
[post]
2018
unpublished
Preserved Fulltext
As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth
doi:10.1149/osf.io/3fvqn
fatcat:5yrxqf6sofaajdlldchjm2f2b4