Optimal matrix multiplication on fault-tolerant VLSI arrays

P.J. Varman, I.V. Ramakrishnan
<span title="">1989</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/5jlmyrayyrdazh5awdlsoec77q" style="color: black;">IEEE transactions on computers</a> </i> &nbsp;
The Diogenes methodology, proposed by Rosenberg, for the design of easily testable and configurable fault-tolerant VLSI arrays, results in collinear layouts of processors (PE's) that are configured into the desired array structure by appropriate switch settings on buses running parallel to the PE's. While possessing attractive mechanisms for fault-tolerant implementations, Diogenes designs of two-dimensional (2-D) arrays require more area than a two-dimensional implementation and result in long
more &raquo; ... wires between logically adjacent PE's. In this paper, we present a collinear VLSI array that retains all the desirable fault-tolerance characteristics of Diogenes designs but avoids the degradation in throughput (caused by a lower system clock rate) that long inter-PE wire lengths would impose. Just as in the systolic model, all signals in our array travel a fixed physical distance in any clock cycle. On this model, we show a lower bound of Q(n&) on the time complexity required to multiply two n x n matrices by computing the n3 scalar products. Furthermore, we present an optimal O(n&) time systolic algorithm using n& PE's and requiring O(n*) area. Our algorithm is superior in time performance and/or area requirements to previous matrix multiplication algorithms on this model.
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