MIMO systems (with multiple transmit and receive antennas) are becoming increasingly popular, and many next-generation systems such as WiMAX, 3-GPP LTE and IEEE802.11n wireless LANs rely on the increased throughput of MIMO systems with up to four antennas at receiver and transmitter. High throughput implementation of the detection unit for MIMO systems is a significant challenge. This challenge becomes still harder, because the above mentioned standards demand support for multiple modulation

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... coding schemes. This implies that the MIMO detector must be dynamically reconfigurable. Also, to achieve required Bit Error Rate(BER) or Frame Error Rate (FER) performance, the detector has to provide soft values to advanced Forward Error Correction (FEC) schemes like Turbo Codes. This paper presents an ASIC implementation of a novel MIMO detector architecture that is able to reconfigure on the fly and provides soft values as output. The design is implemented in 45nm predictive technology library [16] , and has a parallelism factor of four. The detector has many qualities of a systolic architecture and achieves a continuous throughput of 1Gbps for QPSK, 500Mbps for 16-QAM, and 187.5Mbps for 64-QAM. The total area is estimated to be approximately 70KGates equivalent, and power consumption is estimated to be 114mW.