A pipelined memory architecture for high throughput network processors

Timothy Sherwood, George Varghese, Brad Calder
2003 Proceedings of the 30th annual international symposium on Computer architecture - ISCA '03  
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture for backbone routers, based on the manipulation of wide irregular memory words, that can provide a feasible design alternative to custom ASICs. We propose a pipelined memory design that emphasizes worst-case throughput over latency, and co-explore architectural tradeoffs with the design of several important network
more » ... rithms. Through this co-exploration, we show that a programmable architecture can efficiently exploit behavior inherent to most common network algorithms to keep up with next generation network speeds.
doi:10.1145/859618.859652 fatcat:gqbkgwedrjd6lhfdut3wyaqhre