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Proceedings of the 15th international symposium on System Synthesis - ISSS '02
Code size is a critical concern in many embedded system applications, especially those using RISC cores. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, spaceefficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature (termed rISA) can potentially reduce the code size by up to 50% with minimaldoi:10.1145/581227.581228 fatcat:xunqyb64grfjtjstx6yvcpmwge