Design Issues for NEM-Relay-Based SRAM Devices

Sebastià A. Bota, Jaume Verd, Xavier Gili, Joan Barceló, Gabriel Torrens, Rafel Perelló, Tomeu Alorda, Carol de Benito, Jaume Segura, N. Mastorakis, V. Mladenov, A. Bulucea
2018 MATEC Web of Conferences  
We analyze the design constraints of six transistor SRAM cells that arise when using nanoelectromechanical relays. Comparisons are performed between a CMOS 6T conventional SRAM cell and various hybrid memory cells built by replacing a selection of MOSFET transistors with NEM relays. Impact on important memory cell parameters such as various reliability metrics like static noise margin and write noise margin and power consumption are evaluated from circuit simulations using a Verilog-A compact
more » ... del of the nanomechanical relay. We found that the use of relays involve a new challenge in the design of SRAM hybrid devices as the readability and writeability of the resulting cells manifests a strong dependence with the value of the contact resistance of the NEM relay, a parameter that can experience important variations with the continued operation of the device.
doi:10.1051/matecconf/201821001005 fatcat:isvfdvlvsvcprhrcudqu7zvstu