Performance and reliability degradation of CMOS Image Sensors in Back-Side Illuminated configuration

Andrea Vici, Felice Russo, Nicola Lovisi, Aldo Marchioni, Antonio Casella, Fernanda Irrera
2020 IEEE Journal of the Electron Devices Society  
We present a systematic characterization of wafer-level reliability dedicated test structures in Back-Side-Illuminated CMOS Image Sensors. Noise and electrical measurements performed at different steps of the fabrication process flow, definitely demonstrate that the wafer flipping/bonding/thinning and VIA opening proper of the Back-Side-Illuminated configuration cause the creation of oxide donor-like border traps. Respect to conventional Front-Side-Illuminated CMOS Image Sensors, the presence
more » ... these traps causes degradation of the transistors electrical performance, altering the oxide electric field and shifting the flat-band voltage, and strongly degrades also reliability. Results from Time-Dependent Dielectric Breakdown and Negative Bias Temperature Instability measurements outline the impact of those border traps on the lifetime prediction. INDEX TERMS Backside CMOS image sensors, gate oxide traps, performance and reliability degradation, noise and charge pumping measurements, lifetime prediction. ANDREA VICI received the M.S. degree (cum laude) in nanotechnology engineering from the Sapienza University of Rome, Italy, in 2018, where he was a Research Fellow on experimental techniques for the study of reliability in VLSI technology in 2019, presenting his results at major conferences, including IEDM and ESSDERC. He is currently pursuing the Ph.D. degree in engineering science with IMEC and Katholieke Universiteit Leuven, Belgium. FELICE RUSSO received the M.S. degree in nuclear physics from the University of Naples Federico II, Italy, in 1990, with a thesis conducted at the CERN of Geneva. In 1996, he joined Texas Instruments, Avezzano, Italy, where he was an Elected Member of Technical Staff (MTS). Since 1998, he has been with Micron Technology, where he became a Senior MTS in 1999. He is currently responsible of data mining, reliability, and device performance teams with LFoundry. His interests and skills are in yield modeling, hot pixels, metallic contamination, machine learning, FDC-PHM, VM, plasma damage, and antenna structures, WLRC, and physics device.
doi:10.1109/jeds.2020.2986729 fatcat:5rde4dk2qze6vdbtx75ocgnbsi