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Performance and reliability degradation of CMOS Image Sensors in Back-Side Illuminated configuration
2020
IEEE Journal of the Electron Devices Society
We present a systematic characterization of wafer-level reliability dedicated test structures in Back-Side-Illuminated CMOS Image Sensors. Noise and electrical measurements performed at different steps of the fabrication process flow, definitely demonstrate that the wafer flipping/bonding/thinning and VIA opening proper of the Back-Side-Illuminated configuration cause the creation of oxide donor-like border traps. Respect to conventional Front-Side-Illuminated CMOS Image Sensors, the presence
doi:10.1109/jeds.2020.2986729
fatcat:5rde4dk2qze6vdbtx75ocgnbsi