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The Impulse memory controller provides an interface for remapping irregular or sparse memory accesses into dense accesses in the cache memory. This capability significantly increases processor cache and system bus utilization, and previous work shows performance improvements from a factor of 1.2 to 5 with current technology models for hand-coded kernels in a cycle-level simulator. To attain widespread use of any specialized hardware feature requires automating its use in a compiler. In thisdoi:10.1109/pact.2001.953295 dblp:conf/IEEEpact/HuangWM01 fatcat:ljoi3goco5f3lo364efhbaubfu