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Warp Processors
2006
ACM Transactions on Design Automation of Electronic Systems
We describe a new processing architecture, known as a warp processor, that utilizes a fieldprogrammable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these improvements completely transparently and operates from a standard binary. A warp processor dynamically detects the binary's critical regions,
doi:10.1145/1142980.1142986
fatcat:sqcy36iw7neqlnmyzvwriwrequ