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Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)
This paper reports two sets of important results in our exploration of an interconnect-centric design ow for deep submicron DSM designs: i We obtain e cient yet accurate wiring area estimation models for optimal wire sizing OWS. We also propose a simple metric to guide area-e cient performance optimization; ii Guided by our interconnect estimation models, we study the interconnect architecture planning problem for wirewidth designs. We achieve a rather surprising result which suggests that twodoi:10.1109/dac.1999.781368 fatcat:uomzlzngavdqpd2j3piweiwxp4