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Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen
[thesis]
1990
1990 \yl/Lr*-r^ compared to the classic fault model and test synthesis approaches.
doi:10.3929/ethz-a-000569425
fatcat:p2dfc53e4feztnhu4r2xf64c4y