A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
Verification of Universal Memory Controller
2017
International Research Journal of Engineering and Technology (IRJET)
unpublished
Preserved Fulltext
This paper describing verification of the Universal Memory Controller (UMC) which is compatible with WISHBONE verification IP .It involves creating a test bench for UMC as DUT. By generating a test cases the UMC features are verified and thus DUT is verified. For the verification of UMC three test cases are used .First test case involving SDRAM, second test case of SSRAM and last test case is of SYNC (synchronous chip select device).
fatcat:2qp5oklrerc57cb4nfqxtk5twu