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Hardware Description Languages and their Applications
In this paper we present a genetic scheduling algorithm to support the synthesis of structured data paths with the aim of producing designs with a predictable layout structure and conserving on-chip wiring resources. The data path is organized as architectural blocks (A-block) with local functional unit (FU), memory elements and internal interconnections. The A-blocks are interconnected by a few global buses. Our scheduling algorithm delivers the schedule of operations, the A-block in whichdoi:10.1007/978-0-387-35064-6_12 fatcat:aq4aulaj7jgbfh4dcsnq3g3i6a