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Architectural design features of a programmable high throughput AES coprocessor
2004
International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004.
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Programmable, high throughput domain specific crypto processors are required for different networking applications. This paper presents the architectural design features that lead to a multiple Gbits/s rate AES coprocessor, which is programmable with domain specific instructions for Gbit throughput IPSec and other applications. Our design is a loosely coupled, independently working crypto-coprocessor that runs AES in ECB, CBC-MAC, Counter, and CCM modes of operation at a maximum throughput of
doi:10.1109/itcc.2004.1286703
dblp:conf/itcc/HodjatSV04
fatcat:dshi4k2jqzgwjkwovoy5bimrx4