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Understanding and Optimizing Power Consumption in Memory Networks
2017
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
As the amount of digital data the world generates explodes, data centers and HPC systems that process this big data will require high bandwidth and high capacity main memory. Unfortunately, conventional memory technologies either provide high memory capacity (e.g., DDRx memory) or high bandwidth (GDDRx memory), but not both. Memory networks, which provide both high bandwidth and high capacity memory by connecting memory modules together via a network of pointto-point links, are promising future
doi:10.1109/hpca.2017.60
dblp:conf/hpca/JianH017
fatcat:dxicua4ppvf6niibxncccznfcm