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A Survey on Steiner Tree Construction and Global Routing for VLSI Design
2020
IEEE Access
Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great
doi:10.1109/access.2020.2986138
fatcat:nqpdbybucjembl4iztn67l4fgi